1. Field of the Invention
This invention relates generally to electronic devices, and more particularly, to designs of diodes and resistive memory devices.
2. Discussion of the Related Art
FIG. 1 illustrates a type of resistive memory device 30. The memory device 30 includes an electrode 32, a switching or active layer 34 on the electrode 32, and an electrode 36 on the switching layer 34. Initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 32, while a positive voltage is applied to electrode 36, so that an electrical potential Vpg is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This causes electronic charge carriers in the form of electrons and/or holes to enter the layer 34, to provide that the overall memory device 30 is in a conductive, low-resistance (programmed) state (A, FIG. 2). Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an on-state resistance illustrated at B.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 130 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device 30, a positive voltage is applied to the electrode 32, while the electrode 36 is held at ground, so that an electrical potential Ver is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36. Application of this electrical potential causes electronic charge carriers to leave the layer 34 (C), switching the layer 34 to a high-resistance state, so that the overall memory device 30 is in a high-resistance (erased) state.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the layer 34 (and memory device 30) in a high-resistance or substantially non-conductive state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
The structure and operation of conventional semiconductor diodes are well known. Typically, a diode 20 is formed by providing adjoining p and n layers 22, 24 of material, to form a p-n junction (FIG. 3). Increasing electrical potential applied across the diode 20 in the forward direction overcomes the threshold voltage Vth of the diode 20, which then conducts current in the forward direction, the level of current being determined by the (relatively low) on-resistance of the diode 20. Increasing electrical potential applied across the diode 20 in the reverse direction does not cause significant conduction of current until breakdown occurs (at a relatively high voltage), whereupon the diode 20 then conducts current in the reverse direction (FIG. 4).
Diodes of this type are used as access devices for resistive memory devices in an array 40 including bit lines BL0, BL1, . . . and word lines WL0, WL1, . . . (FIG. 5). In certain situations, such as when the diodes 20 are used as access devices for resistive memory devices 30 in a three-dimensional memory array (one array layer shown in FIG. 5), where resistive memory devices are already fabricated on a previously formed array layer, a low temperature diode fabrication sequence is needed in order not to alter or destroy the operational characteristics of devices already formed.
As will be understood, improvements in manufacturing and operational efficiency of such a resistive memory device are being sought, particularly when used in a memory array with access diodes associated therewith.
Therefore, what is needed is an approach for improving these devices for these particular needs.